Add bindings for the System-2 clocks and reset generator (SYS2CRG) on JHB100 SoC.
Signed-off-by: Changhuang Liang <[email protected]> --- .../clock/starfive,jhb100-sys2crg.yaml | 64 +++++++++++++++++++ .../dt-bindings/clock/starfive,jhb100-crg.h | 33 ++++++++++ .../dt-bindings/reset/starfive,jhb100-crg.h | 26 ++++++++ 3 files changed, 123 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-sys2crg.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-sys2crg.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-sys2crg.yaml new file mode 100644 index 000000000000..5f71e761be23 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-sys2crg.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jhb100-sys2crg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 System-2 Clock and Reset Generator + +maintainers: + - Changhuang Liang <[email protected]> + +properties: + compatible: + const: starfive,jhb100-sys2crg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (25 MHz) + - description: PLL1 + - description: System-2 GPU0 600MHz + - description: System-2 GPU1 600MHz + + clock-names: + items: + - const: osc + - const: pll1 + - const: sys2_gpu0_600 + - const: sys2_gpu1_600 + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jhb100-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive-jhb100-crg.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@13008000 { + compatible = "starfive,jhb100-sys2crg"; + reg = <0x13008000 0x4000>; + clocks = <&osc>, <&pll1>, <&sys0crg 73>, + <&sys0crg 74>; + clock-names = "osc", "pll1", "sys2_gpu0_600", + "sys2_gpu1_600"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-bindings/clock/starfive,jhb100-crg.h index 510a5c6fa89a..34e4498fc1c8 100644 --- a/include/dt-bindings/clock/starfive,jhb100-crg.h +++ b/include/dt-bindings/clock/starfive,jhb100-crg.h @@ -73,4 +73,37 @@ #define JHB100_SYS1CLK_BMCPER3_100 18 #define JHB100_SYS1CLK_BMCPER3_125 19 +/* SYS2CRG clocks */ +#define JHB100_SYS2CLK_JTAGM0_200 3 +#define JHB100_SYS2CLK_JTAGM1_200 4 +#define JHB100_SYS2CLK_JTAGM0_100 5 +#define JHB100_SYS2CLK_JTAGM1_100 6 +#define JHB100_SYS2CLK_JTAGM0_ATPG_TCLOCK 7 +#define JHB100_SYS2CLK_JTAGM1_ATPG_TCLOCK 8 +#define JHB100_SYS2CLK_JTAG0_MST_WRAP_HCLK 9 +#define JHB100_SYS2CLK_JTAG0_MST_WRAP_CLK_JTAG 10 +#define JHB100_SYS2CLK_JTAG0_MST_WRAP_APB_PCLK 11 +#define JHB100_SYS2CLK_JTAG0_MST_WRAP_ATPG_TCLOCK 12 +#define JHB100_SYS2CLK_JTAG1_MST_WRAP_HCLK 13 +#define JHB100_SYS2CLK_JTAG1_MST_WRAP_CLK_JTAG 14 +#define JHB100_SYS2CLK_JTAG1_MST_WRAP_APB_PCLK 15 +#define JHB100_SYS2CLK_JTAG1_MST_WRAP_ATPG_TCLOCK 16 +#define JHB100_SYS2CLK_HOSTUSB_100 17 +#define JHB100_SYS2CLK_HOSTUSBCMN_500 18 +#define JHB100_SYS2CLK_BMCPER1_200 19 +#define JHB100_SYS2CLK_BMCPER1_250 20 +#define JHB100_SYS2CLK_BMCPER1_143_DFT 21 +#define JHB100_SYS2CLK_BMCPER1_143 22 +#define JHB100_SYS2CLK_BMCPER0_200 23 +#define JHB100_SYS2CLK_GPU0_100 24 +#define JHB100_SYS2CLK_GPU0_BUS_CLK 25 +#define JHB100_SYS2CLK_GPU0_APB_CLK 26 +#define JHB100_SYS2CLK_GPU0_OSC_CLK 27 +#define JHB100_SYS2CLK_GPU1_100 28 +#define JHB100_SYS2CLK_GPU1_BUS_CLK 29 +#define JHB100_SYS2CLK_GPU1_APB_CLK 30 +#define JHB100_SYS2CLK_GPU1_OSC_CLK 31 +#define JHB100_SYS2CLK_MAIN_ICG_EN_JTAG0 32 +#define JHB100_SYS2CLK_MAIN_ICG_EN_JTAG1 33 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h b/include/dt-bindings/reset/starfive,jhb100-crg.h index 9a0ab64abafa..d92bc4c6d830 100644 --- a/include/dt-bindings/reset/starfive,jhb100-crg.h +++ b/include/dt-bindings/reset/starfive,jhb100-crg.h @@ -40,4 +40,30 @@ #define JHB100_SYS1RST_BMCPERIPH3_RSTN_CRG 13 #define JHB100_SYS1RST_BMCPERIPH3_RSTN_BUS 14 +/* SYS2CRG resets */ +#define JHB100_SYS2RST_JTAG0_MST_WRAP_HRESETN 2 +#define JHB100_SYS2RST_JTAG0_MST_WRAP_APB_PRESETN 3 +#define JHB100_SYS2RST_JTAG1_MST_WRAP_HRESETN 4 +#define JHB100_SYS2RST_JTAG1_MST_WRAP_APB_PRESETN 5 + +#define JHB100_SYS2RST_HUSBCMN_HOSTCMN_RSTN_BUS_NCNOC_INIT 8 +#define JHB100_SYS2RST_HUSBCMN_RSTN_HOSTCMN_CRG 9 +#define JHB100_SYS2RST_HUSBCMN_HOSTUSB0_RSTN_BUS_NCNOC_BMC_TARG 10 +#define JHB100_SYS2RST_HUSBCMN_HOSTUSB0_RSTN_BUS_NCNOC_HOST_TARG 11 +#define JHB100_SYS2RST_HUSBCMN_RSTN_BMC_CRG 12 +#define JHB100_SYS2RST_HUSBCMN_RSTN_HOSTUSB0_CRG 13 +#define JHB100_SYS2RST_HUSBCMN_HOSTUSB1_RSTN_BUS_NCNOC_BMC_TARG 14 +#define JHB100_SYS2RST_HUSBCMN_HOSTUSB1_RSTN_BUS_NCNOC_HOST_TARG 15 +#define JHB100_SYS2RST_HUSBCMN_RSTN_HOSTUSB1_CRG 16 +#define JHB100_SYS2RST_BMCPERIPH1_RSTN_CRG 17 +#define JHB100_SYS2RST_BMCPERIPH1_RSTN_BUS 18 +#define JHB100_SYS2RST_BMCPERIPH0_RSTN_CRG 19 +#define JHB100_SYS2RST_BMCPERIPH0_RSTN_BUS 20 +#define JHB100_SYS2RST_GPU0_RSTN_CRG 21 +#define JHB100_SYS2RST_GPU0_RSTN_BUS 22 +#define JHB100_SYS2RST_GPU0_HOST_PCIE_RST_N 23 +#define JHB100_SYS2RST_GPU1_RSTN_CRG 24 +#define JHB100_SYS2RST_GPU1_RSTN_BUS 25 +#define JHB100_SYS2RST_GPU1_HOST_PCIE_RST_N 26 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */ -- 2.25.1
