On Mon, May 04, 2026 at 11:54:11AM +0200, Krzysztof Kozlowski wrote: > On Thu, Apr 30, 2026 at 10:28:40AM +0800, Inochi Amaoto wrote: > > +properties: > > + compatible: > > + const: spacemit,k3-comb-phy > > + > > + reg: > > + maxItems: 1 > > + > > + "#phy-cells": > > + const: 2 > > + description: > > + The first one is phy id, the second one is phy type. > > You could mention here the defines representing supported phy types. >
OK. > > + > > + spacemit,apb-spare: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: > > + Phandle to APB SPARE system controller interface, used for > > + PHY calibration. > > + > > + spacemit,apmu: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + items: > > + - items: > > + - description: phandle of APMU syscon > > + - description: configuration of the PHY lanes > > + description: | > > + Phandle to control PHY mux configuration. The configuration > > + is described as follows: > > + bit 4: 0 - PCIe A x8 mode, 1 - PCIe lane share mode > > + bit 3: 0 - PCIe A x4 mode, 1 - PCIe A x2 and PCIe B x2 mode > > + bit 2: 0 - PCIe C lane 0 is PCIe mode , 1 - USB mode > > + bit 1: 0 - PCIe C lane 1 is PCIe mode , 1 - USB mode > > + bit 0: 0 - PCIe D lane is PCIe mode , 1 - USB mode > > I assume this device k3-comb-phy handles phys for PCIe A, B, C and D? > In fact it handles phys for PCIe A-E. The mux for the phy of PCIe E (the id is 5) is controlled by bit 4. If the comb PHY is in shared mode, the PCIe E always got one lane. I think it is good to add a public link for this configuration, but Spacemit has no opened any document for this publicly.... > > + > > + The bit[3:0] is only valid when bit 4 is 1. > > + > > +required: > > + - compatible > > reg required. > It is fine for me > > + - "#phy-cells" > > + - spacemit,apb-spare > > + - spacemit,apmu > > + > > +additionalProperties: false > > Best regards, > Krzysztof > Regards, Inochi
