+}
+
+static void nt37705_reset(struct nt37705_panel *ctx)
+{
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ usleep_range(10000, 11000);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ usleep_range(5000, 6000);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ usleep_range(10000, 11000);
+}
+
+static int nt37705_on(struct nt37705_panel *ctx)
+{
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
+
+ ctx->dsi->mode_flags |= MIPI_DSI_MODE_LPM;
+
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0,
+ 0x55, 0xaa, 0x52, 0x08, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x1b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xba, 0x18);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x1c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xba,
+ 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x2c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xba,
+ 0x00, 0x01, 0x01, 0x01, 0x00, 0x05, 0x05,
+ 0x05, 0x00, 0x05, 0x05, 0x05, 0x00, 0x00,
+ 0x00, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x3c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xba,
+ 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x0b,
+ 0x0b, 0x00, 0x00, 0x0b, 0x0b, 0x00, 0x00,
+ 0x00, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x4c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xba,
+ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x1d, 0x00, 0x00, 0x00, 0x1d, 0x00, 0x00,
+ 0x00, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x5c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xba,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x6c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xba,
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x0b,
+ 0x77, 0x77, 0x00, 0x00, 0x0b, 0x00, 0x1d,
+ 0x00, 0x1d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x7c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xba,
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x0b,
+ 0x77, 0x77, 0x00, 0x00, 0x0b, 0x00, 0x1d,
+ 0x00, 0x1d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x8c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xba,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x9c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xba,
+ 0x11, 0x11, 0x20, 0x02, 0x00, 0x03, 0x00,
+ 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0xa4);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xba, 0x00, 0xc0, 0x40, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0xa8);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xba,
+ 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22,
+ 0x22);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0xb0);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xba,
+ 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22,
+ 0x22);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0,
+ 0x55, 0xaa, 0x52, 0x08, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc5, 0x15, 0x15, 0x15, 0xdd);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0,
+ 0x55, 0xaa, 0x52, 0x08, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x0e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb5, 0x32);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0,
+ 0x55, 0xaa, 0x52, 0x00, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0xaa, 0x55, 0xa5, 0x80);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x19);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf2, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x1a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf4, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x11);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf8, 0x01, 0x7f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x2d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf8, 0x01, 0x20);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0xaa, 0x55, 0xa5, 0x81);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0x3c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf9, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb, 0x0f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x0f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf5, 0x20);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x0d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb, 0x80);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0xaa, 0x55, 0xa5, 0x83);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x12);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x13);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfd, 0x21);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0xaa, 0x55, 0xa5, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY,
+ 0x20);
+ mipi_dsi_dcs_set_column_address_multi(&dsi_ctx, 0x0000, 0x045b);
+ mipi_dsi_dcs_set_page_address_multi(&dsi_ctx, 0x0000, 0x09b3);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_GAMMA_CURVE, 0x00);
+ mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, 0xbb0d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x04);
+ mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, 0xfe0f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x01, 0x19);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x90, 0x03, 0x03);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x91,
+ 0x89, 0x28, 0x00, 0x0c, 0xd2, 0x00, 0x02,
+ 0x2f, 0x01, 0x18, 0x00, 0x07, 0x09, 0x75,
+ 0x08, 0x34, 0x10, 0xf0);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x30);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x00);
+ mipi_dsi_msleep(&dsi_ctx, 120);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x00);
+ mipi_dsi_msleep(&dsi_ctx, 22);
+
+ return dsi_ctx.accum_err;
+}
+
+static int nt37705_off(struct nt37705_panel *ctx)
+{
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
+
+ ctx->dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
+
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x00);
+ mipi_dsi_msleep(&dsi_ctx, 20);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x00);
+ mipi_dsi_msleep(&dsi_ctx, 120);
+
+ return dsi_ctx.accum_err;
+}
+
+static int nt37705_prepare(struct drm_panel *panel)
+{
+ struct nt37705_panel *ctx = to_nt37705_panel(panel);
+ struct device *dev = &ctx->dsi->dev;
+ struct drm_dsc_picture_parameter_set pps;
+ int ret;
+
+ ret = regulator_bulk_enable(ARRAY_SIZE(nt37705_supplies),
ctx->supplies);
+ if (ret < 0) {