From: George Guo <[email protected]>

Implement arch_jump_opcode_bytes() for LoongArch so that klp checksums
for jump/call instructions with non-relocated destination offsets are
position-independent, mirroring the x86 and arm64 implementations.

Mask out the embedded branch offset while preserving the opcode and the
register operands, which differ per instruction format:

  - B/BL (reg0i26):                  no regs -> 0xfc000000
  - BEQZ/BNEZ/BCEQZ/BCNEZ (reg1i21): keep rj/cj -> 0xfc0003e0
  - JIRL/BEQ/BNE/.../BGEU (reg2i16): keep rj/rd -> 0xfc0003ff

Co-developed-by: Kexin Liu <[email protected]>
Signed-off-by: Kexin Liu <[email protected]>
Signed-off-by: George Guo <[email protected]>
---
 tools/objtool/arch/loongarch/decode.c | 41 +++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/tools/objtool/arch/loongarch/decode.c 
b/tools/objtool/arch/loongarch/decode.c
index 674e4efd138f..12facd0cc8d1 100644
--- a/tools/objtool/arch/loongarch/decode.c
+++ b/tools/objtool/arch/loongarch/decode.c
@@ -432,6 +432,47 @@ unsigned long arch_jump_table_sym_offset(struct reloc 
*reloc, struct reloc *tabl
        }
 }
 
+size_t arch_jump_opcode_bytes(struct objtool_file *file, struct instruction 
*insn,
+                             unsigned char *buf)
+{
+       union loongarch_instruction *code;
+       u32 insn_word;
+
+       insn_word = le32toh(*(u32 *)(insn->sec->data->d_buf + insn->offset));
+       code = (union loongarch_instruction *)&insn_word;
+
+       switch (code->reg0i26_format.opcode) {
+       case b_op:
+       case bl_op:
+               /* reg0i26: 26-bit offset, no register operands */
+               insn_word &= 0xfc000000;
+               break;
+       case beqz_op:
+       case bnez_op:
+       case bceqz_op:          /* == bcnez_op */
+               /* reg1i21: keep opcode + rj/cj at bits[9:5] */
+               insn_word &= 0xfc0003e0;
+               break;
+       case jirl_op:
+       case beq_op:
+       case bne_op:
+       case blt_op:
+       case bge_op:
+       case bltu_op:
+       case bgeu_op:
+               /* reg2i16: keep opcode + rj/rd at bits[9:0] */
+               insn_word &= 0xfc0003ff;
+               break;
+       default:
+               break;
+       }
+
+       insn_word = htole32(insn_word);
+       memcpy(buf, &insn_word, sizeof(insn_word));
+
+       return LOONGARCH_INSN_SIZE;
+}
+
 #ifdef DISAS
 
 int arch_disas_info_init(struct disassemble_info *dinfo)
-- 
2.25.1


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