From: Manish Honap <[email protected]> Add the user-visible interface that exposes a CXL Type-2 device to a VMM through vfio-pci:
VFIO_DEVICE_FLAGS_CXL (bit 9) on vfio_device_info::flags marks the device as CXL. VFIO_DEVICE_INFO_CAP_CXL (id 6) is the capability that carries the HDM-backed memory region index, the CXL component register region index, and the layout of the component register block within the containing PCI BAR. VFIO_REGION_SUBTYPE_CXL identifies the HDM memory region. VFIO_REGION_SUBTYPE_CXL_COMP_REGS identifies the CXL component register shadow. Only the HOST_FIRMWARE_COMMITTED flag is exposed. Other CXL device states stay invisible to userspace at this stage. Signed-off-by: Manish Honap <[email protected]> --- include/uapi/linux/vfio.h | 46 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index 5de618a3a5ee..3707d53c4de5 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -215,6 +215,7 @@ struct vfio_device_info { #define VFIO_DEVICE_FLAGS_FSL_MC (1 << 6) /* vfio-fsl-mc device */ #define VFIO_DEVICE_FLAGS_CAPS (1 << 7) /* Info supports caps */ #define VFIO_DEVICE_FLAGS_CDX (1 << 8) /* vfio-cdx device */ +#define VFIO_DEVICE_FLAGS_CXL (1 << 9) /* vfio-cxl Type-2 device */ __u32 num_regions; /* Max region index + 1 */ __u32 num_irqs; /* Max IRQ index + 1 */ __u32 cap_offset; /* Offset within info struct of first cap */ @@ -257,6 +258,36 @@ struct vfio_device_info_cap_pci_atomic_comp { __u32 reserved; }; +/* + * VFIO_DEVICE_INFO capability for CXL Type-2 passthrough devices. + * Present when VFIO_DEVICE_FLAGS_CXL is set on vfio_device_info::flags. + * + * @flags: VFIO_CXL_CAP_HOST_FIRMWARE_COMMITTED indicates the host CXL + * subsystem committed the endpoint HDM decoder. + * @hdm_region_idx: VFIO region index for the HDM memory region + * (subtype VFIO_REGION_SUBTYPE_CXL). + * @comp_reg_region_idx: VFIO region index for the CXL Component + * Register shadow (subtype VFIO_REGION_SUBTYPE_CXL_COMP_REGS). + * @comp_reg_bar: PCI BAR index that contains the CXL component + * register block. Get-region-info on this BAR returns a + * VFIO_REGION_INFO_CAP_SPARSE_MMAP that excludes the CXL block. + * @comp_reg_offset: byte offset of the CXL component register block + * within @comp_reg_bar. + * @comp_reg_size: byte size of the CXL component register block. + */ +#define VFIO_DEVICE_INFO_CAP_CXL 6 +struct vfio_device_info_cap_cxl { + struct vfio_info_cap_header header; + __u32 flags; +#define VFIO_CXL_CAP_HOST_FIRMWARE_COMMITTED (1 << 0) + __u32 hdm_region_idx; + __u32 comp_reg_region_idx; + __u32 comp_reg_bar; + __u32 __resv; + __u64 comp_reg_offset; + __u64 comp_reg_size; +}; + /** * VFIO_DEVICE_GET_REGION_INFO - _IOWR(VFIO_TYPE, VFIO_BASE + 8, * struct vfio_region_info) @@ -425,6 +456,21 @@ struct vfio_region_gfx_edid { #define VFIO_REGION_SUBTYPE_CCW_SCHIB (2) #define VFIO_REGION_SUBTYPE_CCW_CRW (3) +/* + * sub-types for VFIO_REGION_TYPE_PCI_VENDOR (vendor id 1e98 reserved + * for the CXL Consortium); used by vfio-cxl Type-2 device passthrough. + * + * VFIO_REGION_SUBTYPE_CXL exposes the HDM-backed device memory range + * as a mappable region. The range is allocated by the host CXL + * subsystem and the VMM is expected to mmap() it. + * VFIO_REGION_SUBTYPE_CXL_COMP_REGS exposes the CXL Component Register + * block (read-write via pread()/pwrite() only, no mmap()). The VMM + * reads and writes HDM Decoder Capability registers through this + * shadow region instead of touching hardware directly. + */ +#define VFIO_REGION_SUBTYPE_CXL (1) +#define VFIO_REGION_SUBTYPE_CXL_COMP_REGS (2) + /* sub-types for VFIO_REGION_TYPE_MIGRATION */ #define VFIO_REGION_SUBTYPE_MIGRATION_DEPRECATED (1) -- 2.25.1
