In order to prepare to emit KASAN checks in JITed programs, JIT
compilers need to be aware about whether some load/store instructions
are targeting the bpf program stack, as those should not be monitored
(we already have guard pages for that, and it is difficult anyway to
correctly monitor any kind of data passed on stack).

To support this need, make the BPF verifier mark the instructions
depending on whether they could access or not memory other than stack.
As different states in the verifier could lead to different memory types
for the same access, just marking an instruction as accessing stack only
is not enough (it could be some other memory type in another verifier
state), so the algorithm rather sets by default any load/store
instruction as stack only, and if _any_ state leads to any memory access
type other than PTR_TO_STACK, it overrides this setting. It also takes
care about shifting back the instruction marking in adjust_insn_aux_data
if the verifier patches instructions. However, if the verifier generates
new BPF_ST/BPF_STX/BPF_LDX while patching some instructions, those new
ones are systematically marked as non-stack-accessing: this may
over-instrument a few memory accessing instructions, but it allows
making sure that we will not miss accidentally any.

Signed-off-by: Alexis LothorĂ© (eBPF Foundation) <[email protected]>
---
Changes in v4:
- include BPF_ATOMIC in is_mem_insn
- correctly mark instructions in adjust_insn_aux_data if patch generates
  a single instruction (ie replace an instruction)

Changes in v3:
- drop getter
- drop cBPF handling
- update marking shifting logic to track more precisely orignal
  instructions
- systematically mark newly generated instructions as non-stack
  accessing

Changes in v2:
- invert marking logic to cover possible different reg types when the
  verifier covers different states
- add a best-effort processing for classical bpf programs, inspecting
  directly src and dst registers since we don't have verifier env
- make sure to keep marking in sync with prog when it is patched by
  verifier
---
 include/linux/bpf_verifier.h |  2 ++
 kernel/bpf/fixups.c          | 32 +++++++++++++++++++++++++++++++-
 kernel/bpf/verifier.c        |  9 +++++++++
 3 files changed, 42 insertions(+), 1 deletion(-)

diff --git a/include/linux/bpf_verifier.h b/include/linux/bpf_verifier.h
index 76b8b7627a10..868101ef5002 100644
--- a/include/linux/bpf_verifier.h
+++ b/include/linux/bpf_verifier.h
@@ -723,6 +723,8 @@ struct bpf_insn_aux_data {
        u16 const_reg_map_mask;
        u16 const_reg_subprog_mask;
        u32 const_reg_vals[10];
+       /* instruction can access non-stack memory */
+       bool non_stack_access;
 };
 
 #define MAX_USED_MAPS 64 /* max number of maps accessed by one eBPF program */
diff --git a/kernel/bpf/fixups.c b/kernel/bpf/fixups.c
index f515fc9669ce..feee1f33de9d 100644
--- a/kernel/bpf/fixups.c
+++ b/kernel/bpf/fixups.c
@@ -152,6 +152,18 @@ static int get_callee_stack_depth(struct bpf_verifier_env 
*env,
 }
 #endif
 
+static bool is_mem_insn(struct bpf_insn *insn)
+{
+       if (BPF_CLASS(insn->code) != BPF_ST &&
+           BPF_CLASS(insn->code) != BPF_STX &&
+           BPF_CLASS(insn->code) != BPF_LDX)
+               return false;
+
+       return (BPF_MODE(insn->code) == BPF_MEM ||
+               BPF_MODE(insn->code) == BPF_MEMSX ||
+               BPF_MODE(insn->code) == BPF_ATOMIC);
+}
+
 /* single env->prog->insni[off] instruction was replaced with the range
  * insni[off, off + cnt).  Adjust corresponding insn_aux_data by copying
  * [0, off) and [off, end) to new locations, so the patched range stays zero
@@ -172,8 +184,14 @@ static void adjust_insn_aux_data(struct bpf_verifier_env 
*env,
         */
        data[off].zext_dst = insn_has_def32(insn + off + cnt - 1);
 
-       if (cnt == 1)
+       if (cnt == 1) {
+               /* A non-memory accessing insn could have been replaced by a
+                * memory accessing insn, systematically mark it for non-stack
+                * access
+                */
+               data[off].non_stack_access = is_mem_insn(insn);
                return;
+       }
        prog_len = new_prog->len;
 
        memmove(data + off + cnt - 1, data + off,
@@ -183,7 +201,19 @@ static void adjust_insn_aux_data(struct bpf_verifier_env 
*env,
                /* Expand insni[off]'s seen count to the patched range. */
                data[i].seen = old_seen;
                data[i].zext_dst = insn_has_def32(insn + i);
+               if (i == off + insn_off_in_patch) {
+                       data[i].non_stack_access = data[off + cnt - 
1].non_stack_access;
+                       data[off + cnt - 1].non_stack_access = false;
+               } else if (is_mem_insn(insn + i)) {
+                       data[i].non_stack_access = true;
+               }
        }
+       /*
+        * Last slot instruction could be a newly generated
+        * BPF_ST/BPF_LDX/BPF_STX
+        */
+       if (is_mem_insn(insn + off + cnt - 1) && insn_off_in_patch != cnt - 1)
+               data[off + cnt - 1].non_stack_access = true;
 
        /*
         * The indirect_target flag of the original instruction was moved to 
the last of the
diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c
index 51f7965d42e3..1246ce8f5f0f 100644
--- a/kernel/bpf/verifier.c
+++ b/kernel/bpf/verifier.c
@@ -3144,6 +3144,11 @@ static void mark_indirect_target(struct bpf_verifier_env 
*env, int idx)
        env->insn_aux_data[idx].indirect_target = true;
 }
 
+static void mark_non_stack_access(struct bpf_verifier_env *env, int idx)
+{
+       env->insn_aux_data[idx].non_stack_access = true;
+}
+
 #define LR_FRAMENO_BITS        4
 #define LR_SPI_BITS    6
 #define LR_ENTRY_BITS  (LR_SPI_BITS + LR_FRAMENO_BITS + 1)
@@ -6333,6 +6338,10 @@ static int check_mem_access(struct bpf_verifier_env 
*env, int insn_idx, struct b
                else
                        coerce_reg_to_size_sx(&regs[value_regno], size);
        }
+
+       if (!err && reg->type != PTR_TO_STACK)
+               mark_non_stack_access(env, insn_idx);
+
        return err;
 }
 

-- 
2.54.0


Reply via email to