e.g. the AMD64 pci-gart code sets pages not present to prevent potential
cache coherency problems. When doing this it is probably safer to flush the
caches too. So consider clearing of the present bit as a cache flush indicator.
Note that debug pagealloc marks pages regularly not present either, but it won't
call this because it calls directly into a lower level function.
I have not actually seen failures from this, but it seems safer
to do it this way.
Signed-off-by: Andi Kleen <[EMAIL PROTECTED]>
---
arch/x86/mm/pageattr.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
Index: linux/arch/x86/mm/pageattr.c
===================================================================
--- linux.orig/arch/x86/mm/pageattr.c
+++ linux/arch/x86/mm/pageattr.c
@@ -670,9 +670,16 @@ static int __change_page_attr_set_clr(st
return 0;
}
-static inline int cache_attr(pgprot_t attr)
+static inline int cache_attr(pgprot_t set, pgprot_t clr)
{
- return pgprot_val(attr) &
+ /*
+ * Clearing pages is usually done for cache cohereny reasons
+ * (except for pagealloc debug, but that doesn't call this anyways)
+ * It's safer to flush the caches in this case too.
+ */
+ if (pgprot_val(clr) & _PAGE_PRESENT)
+ return 1;
+ return pgprot_val(set) &
(_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD);
}
@@ -709,7 +716,7 @@ static int change_page_attr_set_clr(unsi
* No need to flush, when we did not set any of the caching
* attributes:
*/
- cache = cache_attr(mask_set);
+ cache = cache_attr(mask_set, mask_clr);
/*
* On success we use clflush, when the CPU supports it to
--
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