On Wed, Jul 15, 2026 at 02:37:47AM -0400, Esteban Urrutia wrote:
> Some SoCs such as SM8475 write data to registers using this offset,
> specifically SW_CTRL2 and MX_CTRL2.
> Add pcs_lane1 offset to V5 offsets to support this.
>
> Signed-off-by: Esteban Urrutia <[email protected]>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 1 +
> 1 file changed, 1 insertion(+)
>
Fixes: 0fd0b31965b0 ("phy: qualcomm: qmp-pcie: add support for SAR2130P")
Reviewed-by: Dmitry Baryshkov <[email protected]>
--
With best wishes
Dmitry
