On Wed, Jul 22, 2026 at 05:51:39AM +0000, Esteban Urrutia wrote: > On 7/22/26 1:34 AM, Dmitry Baryshkov wrote: > > Yes, because the platform has different refclock. > Sorry. I think I've lost the thread on this one. From what I've > understood: > - For this commit, v1.1 tables should be left as is without renaming > them.
Yes, you can add a comment that downstream uses "4nm-v1.1" PLL type at the table or at the PHY definition, if you that it helps in future. > - For the third commit, v1 tables (DP serdes, RBR, HBR, HBR2 and HBR3) > should be added along with a comment in the driver explaining the > reason. A reason should be explained in the commit message. If you think that it helps, add a comment about 4nm-v1. > > Please confirm if my conclusions are correct or if additional changes > will have to be made. > > Regards, > Esteban > -- With best wishes Dmitry
