On Mon, Jul 13, 2026 at 6:33 AM Inochi Amaoto <[email protected]> wrote: > > The KVM RISC-V allows Svadu FWFT for Guest/VM so add this extension > to get-reg-list test. > > Assisted-by: YuanSheng:claude-4.7-opus > Co-developed-by: Quan Zhou <[email protected]> > Signed-off-by: Quan Zhou <[email protected]> > Signed-off-by: Inochi Amaoto <[email protected]>
LGTM. Reviewed-by: Anup Patel <[email protected]> Thanks, Anup > --- > .../selftests/kvm/riscv/get-reg-list.c | 21 +++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c > b/tools/testing/selftests/kvm/riscv/get-reg-list.c > index cb86cb6b3635..94e33b2ee796 100644 > --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c > +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c > @@ -745,6 +745,9 @@ static const char *sbi_fwft_id_to_str(__u64 reg_off) > case 3: return "KVM_REG_RISCV_SBI_FWFT | > KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.enable)"; > case 4: return "KVM_REG_RISCV_SBI_FWFT | > KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.flags)"; > case 5: return "KVM_REG_RISCV_SBI_FWFT | > KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.value)"; > + case 6: return "KVM_REG_RISCV_SBI_FWFT | > KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.enable)"; > + case 7: return "KVM_REG_RISCV_SBI_FWFT | > KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.flags)"; > + case 8: return "KVM_REG_RISCV_SBI_FWFT | > KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.value)"; > } > return strdup_printf("KVM_REG_RISCV_SBI_FWFT | %lld /* UNKNOWN */", > reg_off); > } > @@ -944,6 +947,13 @@ static __u64 sbi_fwft_pointer_masking_regs[] = { > KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | > KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.value), > }; > > +static __u64 sbi_fwft_pte_ad_hw_updating_regs[] = { > + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | > KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT, > + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | > KVM_REG_RISCV_SBI_FWFT | > KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.enable), > + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | > KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.flags), > + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | > KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.value), > +}; > + > static __u64 zicbom_regs[] = { > KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | > KVM_REG_RISCV_CONFIG_REG(zicbom_block_size), > KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | > KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM, > @@ -1259,6 +1269,16 @@ static struct vcpu_reg_list > config_sbi_fwft_pointer_masking = { > }, > }; > > +static struct vcpu_reg_list config_sbi_fwft_pte_ad_hw_updating = { > + .sublists = { > + SUBLIST_BASE, > + SUBLIST_ISA(svade, SVADE), > + SUBLIST_ISA(svadu, SVADU), > + SUBLIST_SBI(fwft_pte_ad_hw_updating, FWFT), > + {0}, > + }, > +}; > + > struct vcpu_reg_list *vcpu_configs[] = { > &config_sbi_base, > &config_sbi_sta, > @@ -1268,6 +1288,7 @@ struct vcpu_reg_list *vcpu_configs[] = { > &config_sbi_mpxy, > &config_sbi_fwft_misaligned_deleg, > &config_sbi_fwft_pointer_masking, > + &config_sbi_fwft_pte_ad_hw_updating, > &config_aia, > &config_fp_f, > &config_fp_d, > -- > 2.55.0 >
