On Fri, 07 Aug 2026 09:46:03 +0200, Luca Weiss wrote:
> I've noticed that the .clk_cbcrs list in multiple clock drivers enable
> the GCC_PCIE_RSCC_CFG_AHB_CLK and GCC_PCIE_RSCC_XO_CLK wrongly.
>
> qcom_branch_set_clk_en() will be called on each entry which will set
> BIT(0) to enable the clock, but this is wrong for these two clocks which
> -- this is also why this is marked RFT -- at least for kaanapali
> needs BIT(20) and BIT(21) set to enable them.
>
> [...]
Applied, thanks!
[1/3] clk: qcom: gcc-eliza: Fix always-enabling PCIE_RSCC clocks
commit: 5ffd02d16f4e2f0566b8f31d5610538987e1944c
[2/3] clk: qcom: gcc-hawi: Fix always-enabling PCIE_RSCC clocks
commit: 62bbf7ed9ad97c17377377aae50b7ea7feb9464e
[3/3] clk: qcom: gcc-kaanapali: Fix always-enabling PCIE_RSCC clocks
commit: 0bfb542fc3368371cefb4cf45ef21c3ba2d37c3f
Best regards,
--
Bjorn Andersson <[email protected]>
