On Thu, Jul 30, 2026, Ewan Hai-oc wrote: > From: Frank Zhu <[email protected]> > > In the test, the ERROR_CODE_EXT_FLAG bit should not be set in the #GP > error code on Zhaoxin CPUs.
Why not? > Add GP_ERROR_CODE_ZX and use it when > running on Zhaoxin hardware. > > Signed-off-by: Frank Zhu <[email protected]> > Signed-off-by: Ewan Hai <[email protected]> > --- > tools/testing/selftests/kvm/x86/nested_exceptions_test.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/tools/testing/selftests/kvm/x86/nested_exceptions_test.c > b/tools/testing/selftests/kvm/x86/nested_exceptions_test.c > index aeec3121c8e8..bacbbdc5dc69 100644 > --- a/tools/testing/selftests/kvm/x86/nested_exceptions_test.c > +++ b/tools/testing/selftests/kvm/x86/nested_exceptions_test.c > @@ -38,6 +38,7 @@ > */ > #define GP_ERROR_CODE_AMD ((SS_VECTOR * 8) | ERROR_CODE_IDT_FLAG) > #define GP_ERROR_CODE_INTEL ((SS_VECTOR * 8) | ERROR_CODE_IDT_FLAG | > ERROR_CODE_EXT_FLAG) > +#define GP_ERROR_CODE_ZX ((SS_VECTOR * 8) | ERROR_CODE_IDT_FLAG) > > /* > * Intel and AMD both shove '0' into the error code on #DF, regardless of > what > @@ -139,7 +140,8 @@ static void l1_vmx_code(struct vmx_pages *vmx) > */ > GUEST_ASSERT_EQ(vmwrite(EXCEPTION_BITMAP, INTERCEPT_SS_GP_DF), 0); > vmx_run_l2(l2_ss_pending_test, SS_VECTOR, (u16)SS_ERROR_CODE); > - vmx_run_l2(l2_ss_injected_gp_test, GP_VECTOR, GP_ERROR_CODE_INTEL); > + vmx_run_l2(l2_ss_injected_gp_test, GP_VECTOR, > + host_cpu_is_zx ? GP_ERROR_CODE_ZX : GP_ERROR_CODE_INTEL); > > GUEST_ASSERT_EQ(vmwrite(EXCEPTION_BITMAP, INTERCEPT_SS_DF), 0); > vmx_run_l2(l2_ss_injected_df_test, DF_VECTOR, DF_ERROR_CODE); > -- > 2.34.1 > >
