On 8/22/26 4:25 AM, David Heidelberg via B4 Relay wrote: > From: David Heidelberg <[email protected]> > > The sdm845 CSIPHY timer clock only listed up to 269.33 MHz, capping the > supported CSI link frequency at roughly 1.07 GHz > (CSIPHY timer = link_freq / 4). The Samsung S5K2X7SP camera runs at a > 1.15 GHz link frequency, so camss rejected powering up the > pipeline with 'Pixel clock is too high for CSIPHY'. > > Add a 288 MHz entry to the shared camcc CSIPHY timer frequency table > (PLL1 VCO 1152 MHz, well within range) and add a 400 MHz entry to the > sdm845 CSIPHY timer clock_rate tables. The camss min_rate check now > passes and the timer clock rounds to 288 MHz, matching the ~287.5 MHz > required by the 1.15 GHz link. > > Assisted-by: tencent:hy3 > Signed-off-by: David Heidelberg <[email protected]> > --- > Tested on SHIFT 6MQ with next-20260820.
Is that what happens on downstream for this device too? Is there a chance the sensor link frequency can be lowered? Generally the latest clock plan for SDM845 says that 269.333 MHz is a maximum, with the RPMHPD running at TURBO.. I would assume that while the PLL rate stays the same, the downstream branches and RCGs may not have been validated to properly function at these freqs Konrad
