From: David Heidelberg <[email protected]> Be more clear with pin description and group all of them into one state.
No functional changes. Signed-off-by: David Heidelberg <[email protected]> --- arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 34 ++++++++++++++-------- 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi index f73d4ea57705f..f1379857e2742 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi @@ -400,17 +400,17 @@ nfc@28 { compatible = "nxp,pn557", "nxp,nxp-nci-i2c"; reg = <0x28>; interrupts-extended = <&tlmm 63 IRQ_TYPE_EDGE_RISING>; enable-gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>; firmware-gpios = <&tlmm 79 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&nfc_int_default &nfc_enable_default>; + pinctrl-0 = <&nfc_default>; pinctrl-names = "default"; }; }; &i2c12 { /* Bottom spkr (right) CS35L36 @ 40 */ /* Top spkr (left) CS35L36 @ 41 */ @@ -473,28 +473,38 @@ &qup_uart9_tx { drive-strength = <2>; bias-disable; }; &tlmm { gpio-reserved-ranges = < 0 4>, /* SPI (Intel MNH Pixel Visual Core) */ <81 4>; /* SPI (most likely Fingerprint Cards FPC1075) */ - nfc_int_default: nfc-int-default-state { - pins = "gpio63"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; + nfc_default: nfc-default-state { + enable-pins { + pins = "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + irq-pins { + pins = "gpio63"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + firmware-pins { + pins = "gpio79"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; - nfc_enable_default: nfc-enable-default-state { - pins = "gpio25", "gpio79"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; }; touchscreen_reset: ts-reset-state { pins = "gpio99"; function = "gpio"; drive-strength = <8>; bias-pull-up; }; -- 2.55.0
