Add helper functions which operate directly on an ESR value rather than trying to access the register itself.
These mirror equivalent KVM vCPU wrappers in kvm_emulate.h and allow those wrappers and KVM's stage-2 fault handling to operate on a plain ESR value. This is needed to later generate a synthetic fault for the stage-2 page table pre-faulting mechanism. No functional change intended. Signed-off-by: Lorenzo Stoakes (ARM) <[email protected]> --- arch/arm64/include/asm/esr.h | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h index f816f5d77f1a..9c0205983d9a 100644 --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -437,6 +437,50 @@ #ifndef __ASSEMBLER__ #include <asm/types.h> +static __always_inline u8 esr_get_ec(unsigned long esr) +{ + return ESR_ELx_EC(esr); +} + +static __always_inline bool esr_trap_is_iabt(unsigned long esr) +{ + return esr_get_ec(esr) == ESR_ELx_EC_IABT_LOW; +} + +static __always_inline bool esr_abt_is_s1ptw(unsigned long esr) +{ + return esr & ESR_ELx_S1PTW; +} + +/* Always check for S1PTW *before* using this. */ +static __always_inline bool esr_dabt_is_write(unsigned long esr) +{ + return esr & ESR_ELx_WNR; +} + +static __always_inline bool esr_dabt_is_cm(unsigned long esr) +{ + return esr & ESR_ELx_CM; +} + +static __always_inline bool esr_abt_is_exec_fault(unsigned long esr) +{ + return esr_trap_is_iabt(esr) && !esr_abt_is_s1ptw(esr); +} + +static __always_inline bool esr_abt_is_sea(unsigned long esr) +{ + switch (esr & ESR_ELx_FSC) { + case ESR_ELx_FSC_EXTABT: + case ESR_ELx_FSC_SEA_TTW(-1) ... ESR_ELx_FSC_SEA_TTW(3): + case ESR_ELx_FSC_SECC: + case ESR_ELx_FSC_SECC_TTW(-1) ... ESR_ELx_FSC_SECC_TTW(3): + return true; + default: + return false; + } +} + static inline unsigned long esr_brk_comment(unsigned long esr) { return esr & ESR_ELx_BRK64_ISS_COMMENT_MASK; -- 2.55.0
