Add Device Tree binding schema for the Allwinner 4-port hardware Message Box controller found on sun55i (A523, A527, T527) and sun60i (A733) SoCs.
The message box connects the ARM Cortex-A55 host cluster to the HiFi4 Audio DSP, Power Management Unit (CPUS), and XuanTie RISC-V co-processor across 12 logical channels with 8-entry hardware FIFOs. Signed-off-by: Tim Michals <[email protected]> --- .../mailbox/allwinner,sun55i-a523-msgbox.yaml | 102 ++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/allwinner,sun55i-a523-msgbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/allwinner,sun55i-a523-msgbox.yaml b/Documentation/devicetree/bindings/mailbox/allwinner,sun55i-a523-msgbox.yaml new file mode 100644 index 000000000000..6b0c7ff70c9f --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/allwinner,sun55i-a523-msgbox.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/allwinner,sun55i-a523-msgbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner sun55i 4-Port Message Box + +maintainers: + - Tim Michals <[email protected]> + - Samuel Holland <[email protected]> + +description: + The hardware message box on sun55i (A523, A527, T527) and sun60i (A733) + SoCs is a 4-port multi-processor mailbox controller connecting the ARM + Cortex-A55 host cluster, HiFi4 Audio DSP, Power Management Unit (CPUS), + and XuanTie RISC-V co-processor. + + It features independent 256-byte register banks for each processor port, + 12 logical channels on the host (4 per remote processor), and 8-entry + hardware FIFOs with level interrupts. + +properties: + compatible: + enum: + - allwinner,sun55i-a523-msgbox + - allwinner,sun55i-t527-msgbox + - allwinner,sun60i-a733-msgbox + + reg: + maxItems: 4 + description: + Register banks for each of the four processor ports. Each port has + an independent 256-byte register bank. + + reg-names: + items: + - const: arm + - const: dsp + - const: cpus + - const: rv + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 4 + description: + One interrupt per processor port in port order (arm, dsp, cpus, rv). + The ARM host port interrupt is required; remote port interrupts are + optional. Use interrupt-names to identify which ports are present when + providing a partial list. + + interrupt-names: + minItems: 1 + maxItems: 4 + items: + enum: + - arm + - dsp + - cpus + - rv + + '#mbox-cells': + const: 1 + description: "channel number (0-11: 0-3 CPUS, 4-7 DSP, 8-11 RISC-V)" + +required: + - compatible + - reg + - reg-names + - clocks + - resets + - interrupts + - '#mbox-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + mailbox@3003000 { + compatible = "allwinner,sun55i-a523-msgbox"; + reg = <0x03003000 0x1000>, + <0x07094000 0x1000>, + <0x07120000 0x1000>, + <0x07136000 0x1000>; + reg-names = "arm", "dsp", "cpus", "rv"; + clocks = <&ccu 120>; + resets = <&ccu 45>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "arm", "dsp", "cpus", "rv"; + #mbox-cells = <1>; + }; -- 2.43.0
