On Mon, Sep 21, 2026 at 07:15:04PM +0800, Zhanpeng Zhang wrote: > From: Clément Léger <[email protected]> > > Register a handler for the local PMU overflow SSE event so that RISC-V > perf can receive overflows even when normal S-mode interrupts are masked. > Reuse the existing overflow handler and pass it the interrupted pt_regs > rebuilt by the architecture SSE entry path. > > Select the delivery mechanism once during PMU probe. Prefer SSE when its > event can be registered and enabled. If the extension or PMU event is > explicitly unsupported, use the ordinary PMU interrupt. Do not enable the > interrupt after any other SSE setup failure or when a crash kernel may > have inherited firmware state. Install the PMU enable and disable > callbacks only after SSE delivery becomes active. > > Keep the local PMU SSE event disabled across CPU power management. On > entry, the generic SSE notifier masks the hart before the lower-priority > PMU notifier disables the event and stops the counters. On exit, the SSE > notifier first unmasks the hart while the event remains disabled. The PMU > notifier then restores counters and event userpage state before enabling > the event. An unmask failure stops the notifier chain and leaves the > counters stopped. Ordinary PMU interrupts retain their existing notifier > ordering. > > An SSE overflow can arrive as soon as the event is enabled during probe. > Publish the counter mask before SSE setup, so an early handler can stop > the counter source even before perf starts admitting normal samples. > After a real overflow, restart only counters whose perf state is still > running. Honor a non-zero return from perf_event_overflow() and leave > throttled events stopped. > > Guest attribution is not part of this version. Detect an interrupted guest > from hstatus.SPV and skip its sample while still updating the period and > counter state, rather than exposing guest state as a host sample. > > The perf PMU callbacks cannot return errors. If an SSE transition or > interrupted-context read fails, latch the failure per CPU and stop its > mapped events through the normal perf state transitions. Do not reset the > firmware counter mapping behind perf, restart a failed event, or attempt a > runtime switch to IRQ delivery. > > During cleanup, close callback admission and synchronously drain each CPU > before disabling and unregistering the SSE event. If firmware refuses the > cleanup, stop the counter source and transfer the event to the SSE core so > later CPU hotplug or shutdown processing can retry without using freed PMU > callback state. > > Signed-off-by: Clément Léger <[email protected]> > Co-developed-by: Himanshu Chauhan <[email protected]> > Signed-off-by: Himanshu Chauhan <[email protected]> > Co-developed-by: Zhanpeng Zhang <[email protected]> > Signed-off-by: Zhanpeng Zhang <[email protected]> > --- > Documentation/arch/riscv/index.rst | 1 + > Documentation/arch/riscv/pmu-sse.rst | 55 +++ > MAINTAINERS | 1 + > drivers/firmware/riscv/riscv_sbi_sse.c | 9 + > drivers/perf/Kconfig | 11 + > drivers/perf/riscv_pmu.c | 14 +- > drivers/perf/riscv_pmu_sbi.c | 540 ++++++++++++++++++++----- > include/linux/perf/riscv_pmu.h | 20 +- > include/linux/riscv_sbi_sse.h | 6 + > 9 files changed, 564 insertions(+), 93 deletions(-) > create mode 100644 Documentation/arch/riscv/pmu-sse.rst
Acked-by: Conor Dooley <[email protected]>
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