On Tuesday 17 July 2012, Jon Masters wrote: > On 07/16/2012 08:16 AM, Pavel Machek wrote: > > >> If an implementation supports AArch32 at EL3 there could be some > >> physical (or some FPGA config) switch to choose between the two. But > >> since AArch64 is mandated, I don't see why one would force AArch32 at > >> EL3 and therefore all lower exception levels (and make a big part of the > >> processor unused). > > > > Actually I see one ... and I can bet it will happen. > > > > So you create that shiny new ARMv8 compliant CPU, 8 cores, 2GHz. HTC > > will want to use it with 1GB of RAM... and put around exiting OMAP > > perihepals. > > But that's why we have Eagle (A15). It's a very capable 32-bit design > from ARM and far more sensible for such designs. You can easily build > something with a few A15 clusters in it, as we're already seeing.
Right, I would say that with any CPU core more powerful than this one or with more than a few of these, you will also have trouble coming up with workloads that really require the CPU performance but don't also require a 64 bit virtual address space in either user space or kernel. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/