The Exynos5 datasheet specifically says that a software reset of SPI must be performed before writing to the PACKET_CNT register. Also, the current code sometimes causes an extra transfer or two to be performed.
Adjust the code slightly to fix this problem. Test flashrom operation on snow. See that SPI operation with ChromeOS EC is reliable now. Signed-off-by: Simon Glass <[email protected]> --- drivers/spi/spi-s3c64xx.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index c34ef8f..3716825 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -213,7 +213,9 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) unsigned long loops; u32 val; - writel(0, regs + S3C64XX_SPI_PACKET_CNT); + val = readl(regs + S3C64XX_SPI_CH_CFG); + val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); + writel(val, regs + S3C64XX_SPI_CH_CFG); val = readl(regs + S3C64XX_SPI_CH_CFG); val |= S3C64XX_SPI_CH_SW_RST; @@ -250,9 +252,7 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); writel(val, regs + S3C64XX_SPI_MODE_CFG); - val = readl(regs + S3C64XX_SPI_CH_CFG); - val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); - writel(val, regs + S3C64XX_SPI_CH_CFG); + writel(0, regs + S3C64XX_SPI_PACKET_CNT); } static void s3c64xx_spi_dmacb(void *data) -- 1.7.7.3 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
