On Wed, 2012-10-17 at 11:35 -0400, Vince Weaver wrote: > > This is by accident; it looks like the code does > val |= ARCH_PERFMON_EVENTSEL_ENABLE; > in p6_pmu_disable_event() so that events are never truly disabled > (is this a bug? should it be &=~ instead?).
I think that's on purpose.. from what I can remember p6 only has a single EN bit (on PMC0) that acts for both counters. So what I did was treat that as a global enable/disable (which it is) and did the local enable/disable by using the NOP events. There really might be bugs in there, its not like I use this class of hardware very frequently (nor do anybody much it seems). -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
