"H. Peter Anvin" <[email protected]> writes: > On 10/22/2012 01:43 PM, Eric W. Biederman wrote: >> >> The reason the BIOSen go wonky is the INIT cause the cpu to go to the >> reset vector at 4G-16 bytes. So it is very much expected that the >> BIOSen start acting like you just came out of reset. >> >> If you can clear bit 8 of IA32_APIC_BASE_MSR and inform the cpu to not >> send the cpu to 4G-16 bytes and instead send the cpu into it's magic >> startup-ipi-wait mode then the BIOSen will not be involved on that path. >> >> It is a simple question of does the cpu support clearing bit 8 >> meaningfully. >> >> If the cpu allows bit 8 to be cleared and sends the cpu to the reset >> vector on receipt of the INIT IPI I would call that a deviation from the >> x86 cpu specification. >> >> So clearing bit 8 is not a question about BIOSen it is a question of can >> we avoid the BIOSen, by using an obscure under-documented cpu feature. >> > > As I said, I thought Fenghua tried that but it didn't work, experimentally.
Fair enough. You described the problem with clearing bit 8 in a weird way. If the best we can muster are fuzzy memories it may be worth revisiting. Perhaps it works on enough cpu models to be interesting. Eric -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
