On Thu, Oct 25, 2012 at 6:11 PM, Murali Karicheri <[email protected]> wrote:
> pll dividers are present in the pll controller of DaVinci and Other > SoCs that re-uses the same hardware IP. This has a enable bit for > bypass the divider or enable the driver. This is a sub class of the > clk-divider clock checks the enable bit to calculare the rate and > invoke the recalculate() function of the clk-divider if enabled. > > Signed-off-by: Murali Karicheri <[email protected]> Looking good, Acked-by: Linus Walleij <[email protected]> Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
