On Thu, Nov 01, 2012 at 11:47:52PM +0000, Luck, Tony wrote:
> > Right, but at least in the csrow case, we still can compute back the
> > csrow even with the interleaving, after we know how it is done exactly
> > (on which address bits, etc). I think this should be doable on Intel
> > controllers too but I don't know.
>
> No. Architecturally all Intel provides is the physical address in MCi_ADDR.
> To do anything with that you are into per-system space, and the
> registers that define the mappings are not necessarily available
> to OS code ... sometimes they are, and sometimes they are even
> documented in places where Mauro can use them to write an
> EDAC driver ... but there are no guarantees.
One more reason that we need some sort of tables telling us which
rank/csrow maps to which DIMM and thus silkscreen label so that we can
be able to say the following from software:
"You just had a single corrected ECC error in the DIMM with label
P0_DIMM_A"
or whatever unique naming each platform vendor comes up with.
The day hw people give me this, I'm going to throw a big party and
invite all LKML.
--
Regards/Gruss,
Boris.
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