On Thu, Jan 31, 2013 at 11:23:53AM -0500, Anson Huang wrote: > some of anatop's regulators(cpu, vddpu and vddsoc) have > register settings about LDO's step time, which will impact > the LDO ramp up speed, need to use set_voltage_time_sel > interface to add necessary delay everytime LDOs' voltage > is increased. > > offset 0x170: > bit [24-25]: cpu > bit [26-27]: vddpu > bit [28-29]: vddsoc > > field definition: > 0'b00: 64 cycles of 24M clock; > 0'b01: 128 cycles of 24M clock; > 0'b02: 256 cycles of 24M clock; > 0'b03: 512 cycles of 24M clock; > > Signed-off-by: Anson Huang <b20...@freescale.com>
Acked-by: Shawn Guo <shawn....@linaro.org> -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
