> > + /* CLK_DIV max is 256 */
> > + for (i = 0; i < 256; i++) {
> > + utemp1 = utemp0 / (i + 1);
> > + /* SCLK_L/H max is 256 / 2 */
> > + if (utemp1 < 128) {
> I think TSCLK_L and TSCLK_H both can be configured upto 255.Why
> limiting it to < 128 ?
> By limiting it to < 128 dont we achieve lesser SCL clock?
Thanks for reviewing but please quote only the relevant part of the
message (like I did). This improves readability a lot.
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