On Mon, 15 Apr 2013, Stephane Eranian wrote: > Never heard of that problem. I know there was another problem due to leaking > during priv level transitions. It would be take a few instr or cycles to > realize > you were not in user level any more when doing event:u. > > Interrupt should impact fixed and generic counters the same way.
Some people inside Intel were reproducing my "deterministic event" work and they informed me of this issue. > Are you sure that the 5th event stayed in fixed counter 0 all along? No, but is there any way to enforce that currently using perf? The results are about what I'd expect. The generic instructions:u events are overcounting by roughly 20,008 for page faults (as expected) and 650 for hardware interrupts (also as expected) wheras the Fixed Counter 0 event is overcounting 10,000 (for page faults?) and undercounting a bit possibly due to a supposedly known issue involving the counts for rep-prefixed string instructions that apparently only happens on Fixed Counter 0. > > $ perf stat -e > > instructions:u,instructions:u,instructions:u,instructions:u,instructions:u > > ./retired_instr.all.x86_64 > > ... > > Performance counter stats for './retired_instr.all.x86_64': > > > > 227,010,687 instructions:u # 0.00 insns per cycle > > 227,010,687 instructions:u # 0.00 insns per cycle > > 227,010,687 instructions:u # 0.00 insns per cycle > > 227,010,687 instructions:u # 0.00 insns per cycle > > 227,000,723 instructions:u # 0.00 insns per cycle > > > > 1.902648316 seconds time elapsed Vince Weaver [email protected] http://www.eece.maine.edu/~vweaver/ -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
