On Tue, Apr 23, 2013 at 02:01:31PM +0800, Axel Lin wrote: > According to the LPC32x0 User Manual [1]: > > For both PWM1 and PWM2 Control Registers: > BIT 31: > This bit gates the PWM_CLK signal and enables the external output pin > to the PWM_PIN_STATE logical level. > > 0 = PWM disabled. (Default) > 1 = PWM enabled > > So in lpc32xx_pwm_enable(), we should set PWM_ENABLE bit. > In lpc32xx_pwm_disable(), we should just clear PWM_ENABLE bit rather than > write 0 to the register which will also clear PWMx_RELOADV and PWMx_DUTY bits. > > [1] http://www.nxp.com/documents/user_manual/UM10326.pdf > > Signed-off-by: Axel Lin <[email protected]> > --- > Hi, > I don't have this hardware handy so I'd appreciate if someone can test this > patch serial. > > This patch serial was sent on https://lkml.org/lkml/2013/3/30/104 > Seems no feedback so far. > So I just try again, maybe someone can help testing it. > Thanks, > Axel
Both patches applied with Roland's Tested-by. Thanks. Thierry
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