Fixing some conditions during BHRB entry processing.
Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com>
---
arch/powerpc/perf/core-book3s.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 09db68d..1de2756 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -1481,25 +1481,25 @@ void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw)
target = val & BHRB_TARGET;
/* Probable Missed entry: Not applicable for POWER8 */
- if ((addr == 0) && (target == 0) && (pred == 1)) {
+ if ((addr == 0) && (!target) && pred) {
r_index++;
continue;
}
/* Real Missed entry: Power8 based missed entry */
- if ((addr == 0) && (target == 1) && (pred == 1)) {
+ if ((addr == 0) && target && pred) {
r_index++;
continue;
}
/* Reserved condition: Not a valid entry */
- if ((addr == 0) && (target == 1) && (pred == 0)) {
+ if ((addr == 0) && target && (!pred)) {
r_index++;
continue;
}
/* Is a target address */
- if (val & BHRB_TARGET) {
+ if (target) {
/* First address cannot be a target address */
if (r_index == 0) {
r_index++;
--
1.7.11.7
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