The P2020 has a non-standard implementation of the SDHCI_HOST_CONTROL
register. This patch adds a QUIRK in the SDHCI header to signal that
a host controller has a non-standard SDHCI_HOST_CONTROL register. The
patch adds a check to the function esdhc_writeb in file
sdhci-of-esdhc.c, where it checks if the write is done to the
SDHCI_HOST_CONTROL register and th host has the above mentioned QUIRK,
then the function simply returns instead of writing to the register.
The patch also detects if the processor is P2020 (by looking in dev
tree) and if so, adds the QUIRK to the host->quirk2
Signed-off-by: Oded Gabbay <ogab...@advaoptical.com>
---
drivers/mmc/host/sdhci-of-esdhc.c | 10 ++++++++++
include/linux/mmc/sdhci.h | 2 ++
2 files changed, 12 insertions(+)
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c
b/drivers/mmc/host/sdhci-of-esdhc.c
index 6f433b8..e70f22f 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -82,6 +82,11 @@ static void esdhc_writeb(struct sdhci_host *host, u8 val,
int reg)
if (reg == SDHCI_HOST_CONTROL) {
u32 dma_bits;
+ /* If host control register is not standard, exit
+ * this function */
+ if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL)
+ return;
+
/* DMA select is 22,23 bits in Protocol Control Register */
dma_bits = (val & SDHCI_CTRL_DMA_MASK) << 5;
clrsetbits_be32(host->ioaddr + reg , SDHCI_CTRL_DMA_MASK << 5,
@@ -210,6 +215,11 @@ static int __devinit sdhci_esdhc_probe(struct
platform_device *pdev)
if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {
/* P2020 has capability of 8 bit bus width */
host->mmc->caps |= MMC_CAP_8_BIT_DATA;
+
+ /* Freescale messed up with P2020 as it has a non-standard
+ * host control register
+ */
+ host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL;
}
ret = sdhci_add_host(host);
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index e9051e1..2742134 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -91,6 +91,8 @@ struct sdhci_host {
unsigned int quirks2; /* More deviations from spec. */
#define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0)
+/* Controller has a non-standard host control register */
+#define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<1)
int irq; /* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
--
1.7.11.7
--
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