On Fri, Jun 07, 2013 at 09:38:10AM +0000, Paul Walmsley wrote:
> +static int get_cvb_voltage(struct platform_device *pdev, int c0, int c1,
> + int c2)
> +{
> + struct tegra_dfll *td = dev_get_drvdata(&pdev->dev);
> + /* apply only speedo scale: output mv = cvb_mv * v_scale */
> + int mv;
> +
> + /* combined: apply voltage scale and round to cvb alignment step */
> + mv = DIV_ROUND_CLOSEST(c2 * td->speedo_value, td->cvb_speedo_scale);
> + mv = DIV_ROUND_CLOSEST((mv + c1) * td->speedo_value,
> + td->cvb_speedo_scale) + c0;
> +
> + /* XXX Bring back cvb_alignment_uv; put it in the board dfll DT */
> + return DIV_ROUND_UP(mv * 1000,
> + td->cvb_voltage_scale * td->vdd_step) *
> + td->vdd_step / 1000;
> +}Hrm, right. So I guess for this the question is why you need the steps at all - can't the driver just ask for the voltage it wants with whatever tolerance is appropriate (or just specify the maximum tolerable voltage if that's better)? I'm not sure what cvb_voltage_scale is. I guess the problem here is that you have to hit some fairly tight tolerances on the voltage?
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