On 10/28/2013 11:06 AM, Henrique de Moraes Holschuh wrote: > On Mon, 28 Oct 2013, Borislav Petkov wrote: >> So Prarit, please split this patch into changes which *directly* address >> the issue and other cleanups ontop. This will simplify review immensely >> as having one single bulky patch is not easy on the eyes. >> >> Then, make sure to audit the lowlevel drivers whether they're already >> issuing output on the error path before adding new printks arbitrarily. > > Something else I couldn't check just from the description (and I apologise, > but I did not look at your patch closely enough to check how you implemented > the functionality on Intel): in the general case, it is NOT acceptable to > bail out if you cannot find the firmware for the first processor. > Mixed-stepping systems do exist, and you might need to update the microcode > of, e.g, just the third processor. > > AMD can get away with a half-done implementation of negative caching (or an > "optimised one" depending on your PoV :) ) because they have per-family > firmware files, so even mixed-stepping systems will require only the same > file. This is *not* true for Intel, which is really annoying.
Is that right? :( I took Andi's comment to imply otherwise ... If that's the case then, yeah, back to the drawing board with this. Andi (or anyone from Intel) -- care to offer a comment? P. > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
