On Wed, 2005-02-09 at 15:06 -0800, Andrew Morton wrote: > Paul Mackerras <[EMAIL PROTECTED]> wrote: > > > > POWER5 machines have a per-hardware-thread register which counts at a > > rate which is proportional to the percentage of cycles on which the > > cpu dispatches an instruction for this thread (if the thread gets all > > the dispatch cycles it counts at the same rate as the timebase > > register). This register is also context-switched by the hypervisor. > > Thus it gives a fine-grained measure of the actual cpu usage by the > > thread over time. > > > > This patch adds code to read this register every timer interrupt and > > on every context switch. > > fyi: This patch consumes another entry from thread_struct.pad[]. > ppc64-implement-a-vdso-and-use-it-for-signal-trampoline.patch consumes two > more entries, so with both patches, you have none left.
Why couldn't we extend the structure ? That would at worse break modules binary compatibility, who cares ? :) Those pads are just stuff that aren't used any more, and back then, when removing them, we did care about modules binary compat... Anyways, I don't think there's anything to worry about at this point. Paul ? Ben. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
