> > So let's just ignore the clearance of these bits in isr(). > > > > +++++ > > SAI Transmit Control Register (I2S1_TCSR) : 32 : R/W : 0000_0000h > > I'm talking about FWF and FRF bits, not TCSR as a register. > > > ----- > > > > I have checked in the Vybrid and LS1 SoC datasheets, and they are all the > > Same as above, and nothing else. > > > > Have I missed ? > > What i.MX IC team told me is SAI ignores what we do to FWF and FRF, so you > don't need to worry about it at all unless Vybrid makes them writable, in > which case we may also need to clear these bits and confirm with Vybrid IC > team if they're also W1C. >
Well, if so, that's fine. Thanks, -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
