On 04/08/2014 06:34 PM, Luck, Tony wrote: >>> Btw, this driver is polling, AFAICT. Doesn't e3-12xx support the CMCI >>> interrupt which you can feed into this driver directly and thus not need >>> the polling at all? >> On the system with the ce and ue events that I'm testing on, I don't see >> 'MCE' nudge above 0, in /proc/interrupts. So I think that implies that >> we are not getting any CMCI there? > CMCI will bump up the "THR" (Threshold) entries in /proc/interrupts.
Ok, so on the system with ue and ce events (as reported by driver and confirmed with a memory scanner), "THR" is 0 across all cpus, and I see no machine checks in the logs... >> So if possible maybe we can confirm with Intel whether we expect an MCE >> for memory errors... > MCG_CAP bit 10 tells you whether a given processor implements CMCI. > If that is set - then MCi_CTL2 bit 30 indicates whether a given bank > supports it (Linux tries to set this bit, if it sticks, then it knows that > CMCI > is supported - Linux also assigns ownership of the bank to the first cpu > to successfully set it (since a bank may be shared by multiple threads/cores > on a package). > > Consumed uncorrectable errors should generate a machine check. Which > on the E3-12xx series will be a fatal machine check: MCi_STATUS.PCC=1 > > -Tony > Hmmm...as I said, I'm not getting any machine checks with ue errors. I've got a fairly old kernel on the system atm, I will try loading a newer kernel, to see if that makes any difference... Thanks, -Jason -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/