Hi Pranith, On Mon, Apr 14, 2014 at 07:45:22PM +0100, Pranith Kumar wrote: > Please disregard previous patches. This is the correct one. > > prefetch destination as is being done in ARM32 atomic ops
Whilst this looks like a potentially sensible optimisation (based on the results I saw on AArch32), I don't think we can take this patch without some benchmarks on real silicon. The interaction between the half-barrier atomic instructions and prfm isn't immediately obvious to me, and we should also consider looking at streaming preload vs the l1keep option. Did you write this patch as a basic port of the arch/arm/ patches I wrote, or was it based on performance figures from real hardware? Will -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
