> > Hi, > > On Wed, May 14, 2014 at 07:00:59AM +0000, Chew, Chiau Ee wrote: > > Heikki, > > For ACPI mode, the clock rate information for PWM is being setup in the > acpi_lpss.c layer. > > Thus, only PCI mode depends on the driver_data to pass in the clock rate > information. > > The goal with this patch is actually to free acpi_lpss.c from delivering the > clock > for this driver. > > The LPSS PWM does not get it's clock from the LPSS 100Mhz source clock, > which means we have to have the rate of it's clock hard-coded. > Since it's already hard coded also in this driver for PCI mode in any case, it > makes no sense to also have it there. > > So this patch will allow us to cleanup acpi_lpss.c. We can now remove the > confusing "shared clock" structure where the hard coded rates are held. This > device is the only one that would need it. >
Oh ya...you are right. Sorry about that. I have mixed up the context with other I/O components. Reviewed-by: Chew, Chiau Ee <chiau.ee.c...@intel.com> > > Thanks, > > -- > heikki -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
