This short series of patches improves the event contraint
tables for Intel SNB, IVB and HSW processors.
1/ removes unnecessary constraints on the Load Latency event
The constraint to counter 3 is not needed. The events works
well on any PEBS-capable counter. The artificial constraint on
counter 3, was used to simplify event scheduling because the
event uses an extra MSR which is ahred by all the counters.
But perf_events can managed shared regs without artificial
counter constraints.
2/ remove unecessary constraint on precise store on HSW
On SNB,IVB, the precise store event has to be on counter 3.
On HSW, precise store is not implemented the same way and
can use any counter. Thus we lift the constraint on all
precise store events on HSW.
The advantage of this series is that it allows capturing load
latency and precise store events at the same time without
multiplexing.
Stephane Eranian (2):
perf/x86: update Haswell PEBS event constraints
perf/x86: fix constraint for load latency and precise store event
arch/x86/kernel/cpu/perf_event_intel.c | 2 --
arch/x86/kernel/cpu/perf_event_intel_ds.c | 22 ++++++++--------------
2 files changed, 8 insertions(+), 16 deletions(-)
--
1.7.9.5
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