> Jeff pointed out several PCI posting errors last time. Before we used > udelay and now we changed to readb/readl instead of udelay this time. > But we only used PCI posting when we think maybe delay there. > So we have to do PCI posting on every writeb? not every
> Do you have some rules for > doing PCI posting while writeb? depends on what kind of registers? basically you need to do posting flushes after every write for which you assume later on the hardware received the write. If you do 5 writes in a row you don't need 5 flushes. If you do a read later always anyway you don't need any flushes. On the other side of the spectrum: if you do something to the hardware and then wait for some event, you do need to flush that stuff. So at minimum you want to make sure that at any point where you leave the driver (to userspace or tty layer or ...) all writes have been flushed. And at all points where you are going to wait for hardware events. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/