On Tue, Sep 02, 2014 at 11:34:29PM -0400, Pranith Kumar wrote:
> Correct the example of memory orderings in memory-barriers.txt
>
> Commit 615cc2c9cf95 "Documentation/memory-barriers.txt: fix important typo re
> memory barriers" changed the assignment to x and y. Change the rest of the
> example to match this change.
>
> Reported-by: Ganesh Rapolu <[email protected]>
> Signed-off-by: Pranith Kumar <[email protected]>
Queued, thank you!
Thanx, Paul
> ---
> Documentation/memory-barriers.txt | 22 +++++++++++-----------
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/Documentation/memory-barriers.txt
> b/Documentation/memory-barriers.txt
> index a4de88f..02f5de8 100644
> --- a/Documentation/memory-barriers.txt
> +++ b/Documentation/memory-barriers.txt
> @@ -121,22 +121,22 @@ For example, consider the following sequence of events:
> The set of accesses as seen by the memory system in the middle can be
> arranged
> in 24 different combinations:
>
> - STORE A=3, STORE B=4, x=LOAD A->3, y=LOAD B->4
> - STORE A=3, STORE B=4, y=LOAD B->4, x=LOAD A->3
> - STORE A=3, x=LOAD A->3, STORE B=4, y=LOAD B->4
> - STORE A=3, x=LOAD A->3, y=LOAD B->2, STORE B=4
> - STORE A=3, y=LOAD B->2, STORE B=4, x=LOAD A->3
> - STORE A=3, y=LOAD B->2, x=LOAD A->3, STORE B=4
> - STORE B=4, STORE A=3, x=LOAD A->3, y=LOAD B->4
> + STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
> + STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
> + STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
> + STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4
> + STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3
> + STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4
> + STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4
> STORE B=4, ...
> ...
>
> and can thus result in four different combinations of values:
>
> - x == 1, y == 2
> - x == 1, y == 4
> - x == 3, y == 2
> - x == 3, y == 4
> + x == 2, y == 1
> + x == 2, y == 3
> + x == 4, y == 1
> + x == 4, y == 3
>
>
> Furthermore, the stores committed by a CPU to the memory system may not be
> --
> 2.1.0
>
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