On Fri, 2014-09-12 at 15:33 -0400, Konrad Rzeszutek Wilk wrote:
> > - /* Set PWT to Write-Combining. All other bits stay the same */
> > - /*
> > - * PTE encoding used in Linux:
> > - * PAT
> > - * |PCD
> > - * ||PWT
> > - * |||
> > - * 000 WB _PAGE_CACHE_WB
> > - * 001 WC _PAGE_CACHE_WC
> > - * 010 UC- _PAGE_CACHE_UC_MINUS
> > - * 011 UC _PAGE_CACHE_UC
>
>
> I think having this nice picture would be beneficial to folks
> who want to understand it. And now you can of course expand it with
> the slot 7 usage.
OK, I will try to preserve the picture.
> > - * PAT bit unused
> > - */
> > - pat = PAT(0, WB) | PAT(1, WC) | PAT(2, UC_MINUS) | PAT(3, UC) |
> > - PAT(4, WB) | PAT(5, WC) | PAT(6, UC_MINUS) | PAT(7, UC);
> > + if ((c->x86_vendor == X86_VENDOR_INTEL) &&
> > + (((c->x86 == 0x6) && (c->x86_model <= 0xd)) ||
> > + ((c->x86 == 0xf) && (c->x86_model <= 0x6)))) {
> > + /*
> > + * Intel Pentium 2, 3, M, and 4 are affected by PAT errata,
> > + * which makes the upper four entries unusable. We do not
> > + * use the upper four entries for all the affected processor
> > + * families for safe.
> > + *
> > + * PAT 0:WB, 1:WC, 2:UC-, 3:UC, 4-7:unusable
> > + *
> > + * NOTE: When WT or WP is used, it is redirected to UC- per
> > + * the default setup in __cachemode2pte_tbl[].
> > + */
> > + pat = PAT(0, WB) | PAT(1, WC) | PAT(2, UC_MINUS) | PAT(3, UC) |
> > + PAT(4, WB) | PAT(5, WC) | PAT(6, UC_MINUS) | PAT(7, UC);
> > + } else {
> > + /*
> > + * WT is set to slot 7, which minimizes the risk of using
>
> You say slot 7 here, but the title of the patch says slot 4?
Oops! I will fix the title.
Thanks for reviewing!
-Toshi
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