There is not need to restore r10, r11 and cr registers at this end of ITLBmiss
handler as they are saved again to the same place in ITLBError handler we are
jumping to.

Signed-off-by: Christophe Leroy <[email protected]>

---
Changes in v2:
- None

Changes in v3:
- None

 arch/powerpc/kernel/head_8xx.S |    8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index bb7c816..e21f0b2 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -381,8 +381,7 @@ InstructionTLBMiss:
        lwz     r3, 8(r0)
 #endif
        mfspr   r10, SPRN_SPRG_SCRATCH2
-       EXCEPTION_EPILOG_0
-       b       InstructionTLBError
+       b       InstructionTLBError1
 
        . = 0x1200
 DataStoreTLBMiss:
@@ -471,7 +470,10 @@ DataStoreTLBMiss:
  */
        . = 0x1300
 InstructionTLBError:
-       EXCEPTION_PROLOG
+       EXCEPTION_PROLOG_0
+InstructionTLBError1:
+       EXCEPTION_PROLOG_1
+       EXCEPTION_PROLOG_2
        mr      r4,r12
        mr      r5,r9
        EXC_XFER_LITE(0x1300, handle_page_fault)
-- 
1.7.1

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