On Fri, 24 Oct 2014, Andy Lutomirski wrote: > Context switches and TLB flushes can change individual bits of CR4. > CR4 reads take several cycles, so store a shadow copy of CR4 in a > per-cpu variable. > > To avoid wasting a cache line, I added the CR4 shadow to > cpu_tlbstate, which is already touched in switch_mm. The heaviest > users of the cr4 shadow will be switch_mm and __switch_to_xtra, and > __switch_to_xtra is called shortly after switch_mm during context > switch, so the cacheline is likely to be hot. > > Signed-off-by: Andy Lutomirski <[email protected]>
Reviewed-by: Thomas Gleixner <[email protected]> -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
