fr den 29.04.2005 Klokka 10:14 (-0400) skreiv Benjamin LaHaise: > On Fri, Apr 29, 2005 at 10:44:17AM +1000, Paul Mackerras wrote: > > You have made semaphores bigger and slower on the architectures that > > have load-linked/store-conditional instructions, which is at least > > ppc, ppc64, sparc64 and alpha. Did you take the trouble to understand > > the ppc semaphore implementation? > > The ppc implementation does have some good ideas that are worth using. > It's hard to know which of the 23 versions were worth using, but I'm > getting a picture where at least 2 variants are need. The atomic ops > variant should use the single counter as ppc does (why did nobody port > that to x86?). A spinlock version is needed at least by parisc.
The PPC implementation would be hard to port to x86, since it relies on the load-linked/store-conditional stuff to provide a fast primitive for atomic_dec_if_positive(). The only way I found to implement that on x86 was to use cmpxchg. On my machine, therefore, a spinlock-based semaphore implementation turns out to be at least as fast for the "fast" path (and is naturally much more efficient for the slow path). Cheers, Trond -- Trond Myklebust <[EMAIL PROTECTED]>
