Hello, On Thu, Jan 22, 2015 at 02:22:58PM +0900, Masahiro Yamada wrote: > As ARM ARM says, the bit 19-16 of ID_MMFR1 is always 0b0000 because > ARMv7 requires a hierarchical cache implementation. > The line "mcr p15, 0, r10, c7, c14, 0" is not reachable. > > Moreover, the v7_flush_dcache_all in arch/arm/mm/cache-v7.S does not > check the ID_MMFR1. > > Signed-off-by: Masahiro Yamada <[email protected]> I stumbled about this some time ago, too. The thing is however that the __armv7_mmu_cache functions are selected if CPUID & 0x000f0000 == 0x000f0000, and that is (AFAIK at present only theoretically) not implying that we have an ARMv7 machine. Only that it uses the "CPUID Identification Scheme" which is required on ARMv7.
Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | http://www.pengutronix.de/ | -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
