The ADC clock frequency is limited depending on modes used. Add
device tree property which allow to set the mode used and the
maximum frequency ratings for the instance. These allows to
set the ADC clock to a frequency which is within specification
according to the actual mode used.
Acked-by: Fugang Duan <b38...@freescale.com>
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
arch/arm/boot/dts/vfxxx.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index a29c7ce..c6609bd 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -189,6 +189,8 @@
clocks = <&clks VF610_CLK_ADC0>;
clock-names = "adc";
status = "disabled";
+ fsl,adck-max-frequency = <30000000>, <40000000>,
+ <20000000>;
};
wdoga5: wdog@4003e000 {
@@ -387,6 +389,8 @@
clocks = <&clks VF610_CLK_ADC1>;
clock-names = "adc";
status = "disabled";
+ fsl,adck-max-frequency = <30000000>, <40000000>,
+ <20000000>;
};
esdhc1: esdhc@400b2000 {
--
2.3.3
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