* Linus Torvalds <[email protected]> wrote:
> On Fri, Mar 27, 2015 at 1:53 PM, Brian Gerst <[email protected]> wrote:
> >> <-- IRQ. Boom
> >
> > The sti will delay interrupts for one instruction, and that should include
> > NMIs.
>
> Nope. Intel explicitly documents the NMI case only for mov->ss and popss.
>
> > The Intel SDM states for STI:
> > "The IF flag and the STI and CLI instructions do not prohibit the
> > generation of exceptions and NMI interrupts. NMI
> > interrupts (and SMIs) may be blocked for one macroinstruction following an
> > STI."
>
> Note the *may*. For movss and popss the software developer guide
> explicitly says that NMI's are also blocked.
>
> For plain sti, it seems to be dependent on microarchitecture.
Well, how about 'STI+HLT' aka safe_halt()?
If an NMI is allowed after that STI then we might lose wakeups, or in
extreme cases (with full-dynticks) might lock up for a long time until
the next irq comes, even with runnable tasks around?
Arguably that's a race condition that is not very easy to notice on a
typical system.
Random hypothesis: maybe Intel just messed up their STI shadow in a
single (possibly ancient) microarchitecture in some rare situations
and figured it could fix it cheaply via updating the documentation to
match the breakage, not via actually fixing the CPU?
Might be useful if someone from Intel could chime in.
Thanks,
Ingo
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