Commit-ID: f4d9757ca6f5a2db6919a5b1ab86b8afa16773d0 Gitweb: http://git.kernel.org/tip/f4d9757ca6f5a2db6919a5b1ab86b8afa16773d0 Author: Thomas Gleixner <[email protected]> AuthorDate: Tue, 19 May 2015 00:00:50 +0000 Committer: Ingo Molnar <[email protected]> CommitDate: Wed, 27 May 2015 09:17:38 +0200
perf/x86/intel/cqm: Document PQR MSR abuse The CQM code acts like it owns the PQR MSR completely. That's not true because only the lower 10 bits are used for CQM. The upper 32 bits are used for the 'CLass Of Service ID' (CLOSID). Document the abuse. Will be fixed in a later patch. Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Acked-by: Matt Fleming <[email protected]> Cc: Kanaka Juvva <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Vikas Shivappa <[email protected]> Cc: Will Auld <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Ingo Molnar <[email protected]> --- arch/x86/kernel/cpu/perf_event_intel_cqm.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_event_intel_cqm.c b/arch/x86/kernel/cpu/perf_event_intel_cqm.c index e4d1b8b..572582e 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_cqm.c +++ b/arch/x86/kernel/cpu/perf_event_intel_cqm.c @@ -978,7 +978,12 @@ static void intel_cqm_event_start(struct perf_event *event, int mode) WARN_ON_ONCE(state->rmid); state->rmid = rmid; - wrmsrl(MSR_IA32_PQR_ASSOC, state->rmid); + /* + * This is actually wrong, as the upper 32 bit MSR contain the + * closid which is used for configuring the Cache Allocation + * Technology component. + */ + wrmsr(MSR_IA32_PQR_ASSOC, rmid, 0); raw_spin_unlock_irqrestore(&state->lock, flags); } @@ -998,7 +1003,13 @@ static void intel_cqm_event_stop(struct perf_event *event, int mode) if (!--state->cnt) { state->rmid = 0; - wrmsrl(MSR_IA32_PQR_ASSOC, 0); + /* + * This is actually wrong, as the upper 32 bit of the + * MSR contain the closid which is used for + * configuring the Cache Allocation Technology + * component. + */ + wrmsr(MSR_IA32_PQR_ASSOC, 0, 0); } else { WARN_ON_ONCE(!state->rmid); } -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
