On Fri, Jun 05, 2015 at 04:35:19PM +1000, Alexey Kardashevskiy wrote: > TCE tables might get too big in case of 4K IOMMU pages and DDW enabled > on huge guests (hundreds of GB of RAM) so the kernel might be unable to > allocate contiguous chunk of physical memory to store the TCE table. > > To address this, POWER8 CPU (actually, IODA2) supports multi-level > TCE tables, up to 5 levels which splits the table into a tree of > smaller subtables. > > This adds multi-level TCE tables support to > pnv_pci_ioda2_table_alloc_pages() and pnv_pci_ioda2_table_free_pages() > helpers. > > Signed-off-by: Alexey Kardashevskiy <[email protected]>
Reviewed-by: David Gibson <[email protected]> -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson
pgpwKbRpGjQqg.pgp
Description: PGP signature
