* Ingo Molnar <[email protected]> wrote:
>
> * Andy Lutomirski <[email protected]> wrote:
>
> > On Mon, Jun 15, 2015 at 2:42 PM, H. Peter Anvin <[email protected]> wrote:
> > > On 06/15/2015 02:30 PM, Linus Torvalds wrote:
> > >>
> > >> On Jun 12, 2015 2:09 PM, "Andy Lutomirski" <[email protected]
> > >> <mailto:[email protected]>> wrote:
> > >>>
> > >>> Caveat emptor: it also disables SMP.
> > >>
> > >> OK, I don't think it's interesting in that form.
> > >>
> > >> For small cpu counts, I guess we could have per-cpu syscall entry points
> > >> (unless the syscall entry msr is shared across hyperthreading? Some
> > >> msr's are
> > >> per thread, others per core, AFAIK), and it could actually work that way.
> > >>
> > >> But I'm not sure the three cycles is worth the worry and the complexity.
> > >
> > > We discussed the per-cpu syscall entry point, and the issue at hand is
> > > that it
> > > is very hard to do that without with fairly high probability touch
> > > another
> > > cache line and quite possibly another page (and hence a TLB entry.)
>
> ( So apparently I wasn't Cc:ed, or gmail ate the mail - so I can only guess
> from
> the surrounding discussion what this patch does, as my lkml folder is still
> doing a long refresh ... )
Hm, it's nowhere to be found. Could someone please forward me the original
email?
Thanks,
Ingo
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