On Tue, Sep 15, 2015 at 04:14:39PM +0200, Peter Zijlstra wrote:
> On Tue, Sep 15, 2015 at 07:09:22AM -0700, Paul E. McKenney wrote:
> > On Tue, Sep 15, 2015 at 02:48:00PM +0200, Peter Zijlstra wrote:
> > > On Tue, Sep 15, 2015 at 05:41:42AM -0700, Paul E. McKenney wrote:
> > > > > Never mind, the PPC people will implement this with lwsync and that is
> > > > > very much not transitive IIRC.
> > > >
> > > > I am probably lost on context, but...
> > > >
> > > > It turns out that lwsync is transitive in special cases. One of them
> > > > is a series of release-acquire pairs, which can extend indefinitely.
> > > >
> > > > Does that help in this case?
> > >
> > > Probably not, but good to know. I still don't think we want to rely on
> > > ACQUIRE/RELEASE being transitive in general though.
> >
> > OK, I will bite... Why not?
>
> It would mean us reviewing all archs (again) and documenting it I
> suppose. Which is of course entirely possible.
>
> That said, I don't think the case at hand requires it, so lets postpone
> this for now ;-)
True enough, but in my experience smp_store_release() and
smp_load_acquire() are a -lot- easier to use than other barriers,
and transitivity will help promote their use. So...
All the TSO architectures (x86, s390, SPARC, HPPA, ...) support transitive
smp_store_release()/smp_load_acquire() via their native ordering in
combination with barrier() macros. x86 with CONFIG_X86_PPRO_FENCE=y,
which is not TSO, uses an mfence instruction. Power supports this via
lwsync's partial cumulativity. ARM64 supports it in SMP via the new ldar
and stlr instructions (in non-SMP, it uses barrier(), which suffices
in that case). IA64 supports this via total ordering of all release
instructions in theory and by the actual full-barrier implementation
in practice (and the fact that gcc emits st.rel and ld.acq instructions
for volatile stores and loads). All other architectures use smp_mb(),
which is transitive.
Did I miss anything?
Thanx, Paul
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